1. Field
Exemplary embodiments of the present invention relate to a semiconductor device design technology, and more particularly, to a technology related to a repair operation for a memory device.
2. Description of the Related Art
FIG. 1 is a block diagram for explaining a repair operation in a conventional memory device, for example, DRAM.
FIG. 1 illustrates a configuration corresponding to one memory bank inside the memory device. Referring to FIG. 1, the memory device includes a memory cell array 110, a row circuit 120, and a column circuit 130. The memory cell array 110 includes a plurality of memory cells. The row circuit 120 is configured to enable a row (or a word line) selected by a row address R_ADD when a row active signal RACT, activated in response to an active command to enable a word line within the memory cell array 110 and deactivated in response to a precharge command to disable a word line, is activated. The column circuit 130 is configured to access, for example, read or write, data of a column (or a bit line) selected by a column address C-ADD when an internal read command RD or an internal write command WR is activated.
A row fuse circuit 140 is configured to store a row address corresponding to a defective memory cell within the memory cell array 110 as a repair row address REPAIR_R_ADD. A row comparator 150 is configured to compare the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 to a row address R_ADD inputted from outside the memory device. When the repair row address REPAIR_R_ADD coincides with the row address R_ADD, the row comparator 150 controls the row circuit 120 to enable a redundancy word line instead of a word line designated by the row address R_ADD. That is, a row corresponding to the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 is replaced with a redundancy row within the memory cell array 110.
Here, DQs denotes data or data pads.
Conventionally, laser fuses are mainly used as the fuse circuit 140. The laser fuses stores logic high or logic low data depending on whether the fuse is cut or not. The laser fuses may be programmed in a wafer state, and may not be programmed after a wafer is mounted in a package. Furthermore, the laser fuses may not be designed with a small circuit area because of the limit in a line pitch.
In order to overcome such concerns, a programmable storage unit including an E-fuse array circuit, a NAND flash memory, a NOR flash memory, a magnetic random access memory (MRAM), a spin transfer torque magnetic random access memory (STT-MRAM), a resistive random access memory (ReRAM), or a phase change random access memory (PCRAM) as disclosed in U.S. Pat. Nos. 6,904,751, 6,777,757, 6,667,902, 7,173,851, and 7,269,047, is disposed into the memory device, and repair information, for example, fail address, is stored in the programmable storage unit.
FIG. 2 is a block diagram illustrating a memory device including a programmable storage unit for storing repair information.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, a plurality of registers 210_0 to 210_3 provided for the respective banks BK0 to BK3 to store repair information, and a programmable storage unit 201.
The programmable storage unit 201 replaces the fuse circuit 140 shown in FIG. 1. The programmable storage unit 201 stores the repair information corresponding to the banks BK0 to BK3, for example, fail addresses. The programmable storage unit 201 may include any one of an E-fuse array circuit, NAND flash memory, NOR flash memory, MRAM, STT-MRAM, ReRAM, and PCRAM.
The registers 210_0 to 210_3 provided for the respective banks BK0 to BK3 are configured to store the repair information of the corresponding memory banks. That is, the register 210_0 stores the repair information of the memory bank BK0, and the register 210_2 stores the repair information of the memory bank BK2. The registers 210_0 to 210_3 each may include latch circuits, and may store the repair information only while power is supplied. The repair information to be stored in the registers 210_0 to 210_3 may be received from the programmable storage unit 201.
The repair information stored in the programmable storage unit 201 is not directly used, but transferred and stored in the registers 220_0 to 210_3 and then used. Since the programmable storage unit 201 is configured in an array form, a predetermined time is required to call data stored in the programmable storage unit 201. Thus, the data stored in the programmable storage unit 201 may not be directly used to perform a repair operation, so that a boot-up operation is performed to transmit and store the repair information stored in the programmable storage unit 201 into the registers 210_0 to 210_3. After the boot-up operation, the data stored in the registers 210_0 to 210_3 are used to perform the repair operation.
When the fuse circuit 140 configured with a laser fuse is replaced with the programmable storage unit 201 and the registers 210_0 to 210_3, it may be possible to repair additional defects discovered after a wafer state, for example, in a package state.